This invention relates to a signal processing circuit for a solid state imaging device.
Generally, as shown in FIG. 1, a solid state imaging device comprises a horizontal scanner 1 for X position selection, a vertical scanner 2 for Y position selection, and a photosensor array 3 of photodiodes 4 and MOS transistors 5. The MOS transistor 5 constitutes a vertical switch responsive to a vertical scanning pulse which is read out to a signal line 6. The drains of the vertical switches arrayed in Y direction are connected in common to a vertical signal output line 7 which in turn is connected to an output signal line 9 through a MOS transistor 8 serving as a horizontal switch responsive to a horizontal scanning pulse. Accordingly, signals from the photodiodes in two-dimensional matrix are sequentially read out to a output terminal 10 when the switches 5 and 8 are sequentially activated by the pulses delivered out of the horizontal and vertical scanners 1 and 2.
The read-out signal is usually amplified by a pre-amplifier and useless components such as clock signals are eliminated by a low-pass filter so as to produce a video signal.
The signal processing by the pre-amplifier and the low-pass filter is not related to the present invention essentially and will not be described herein.
Generally, in a solid state image sensor and in a camera with a pick-up tube as well, image enhancement is adopted to improve picture sharpness. By this, deterioration of the full frequency response over the entire camera inclusive of an imaging device can be corrected. Typically, in a television camera, the image enhancement is carried out independently in the horizontal and vertical directions. FIG. 2a shows, in block form, a typical image enhancement circuit and FIG. 2b shows signal waveforms appearing in the circuit. For explanation, the image enhancement in the horizontal direction will first be described. A video signal 22 produced from an image sensor 21 during one horizontal period branches off and one of three components is applied to a delay circuit 23. The delay circuit 23 has a delay time which depends on a boost frequency. For a boost frequency of 4 MHz, the delay time may preferably be 125 nS. An output signal 24 from the delay circuit 23 is subtracted by a signal component not passed through the delay circuit at a subtractor 25. An output signal 26 from the subtractor 25 has only leading and trailing horizontal edge portions of the horizontal input video signal. The edge signal 26 is set to a suitable level at a signal level setting device 27 and added with the input signal 22 at an adder 28. With the circuit constructed as above, a video signal 29 whose horizontal edge portions are enhanced can be obtained. The image enhancement in the vertical direction may be accomplished on the basis of the same principle as that of the horizontal image enhancement described previously. More particularly, for the vertical image enhancement, a circuit for delaying the image signal by one horizontal scanning period (about 63.5 .mu.S), hereinafter referred to as a 1 HDL circuit, is used as a delay line. With reference to FIG. 3, it is now assumed that a window pattern 31 on a picture screen is imaged. The window pattern is sampled by the scanning line in the vertical direction and a video signal as shown at section (a) in FIG. 3 is produced. The video signal is passed through the 1 HDL circuit and a signal as shown at section (b) in FIG. 3 is obtained. Then, the original input signal at (a) is subtracted by the output signal at (b) of the 1 HDL circuit and a signal as shown at section (c) in FIG. 3 is obtained. Obviously, the signal at (c) represents a vertical edge signal. In this manner, the vertical image enhancement can be accomplished by replacing the delay circuit with the 1 HDL circuit in the circuit arrangement of FIG. 2. Generally, for the 1 HDL circuit participating in the vertical image enhancement, a crystal delay line (so-called glass delay line) utilizing the propagation time of a crystal or a charge transfer device such as CCD is used.
FIG. 4 shows a 1 HDL circuit utilizing a glass delay line. The glass delay line is based on propagation delay time within glass 44, as described above. Accordingly, when the glass delay line is driven by a transducer 43 for converting an electrical signal into an ultrasonic wave, the ultrasonic wave is delayed and converted into an electrical signal by an acoustoelectric transducer 45. A piezo-electric transducer is typically used as the transducer 45.
With the ultrasonic delay line, the signal must be modulated with a high frequency and applied to the delay line. Accordingly, there needs a modulator 41, an actuator 42 and a carrier wave oscillator 49. Since an output signal from the transducer 45 is terribly attenuated, an amplifier 46 is also provided. An amplified signal is detected by a detector 47, eliminated of the useless carrier-signal by a low-pass filter 48, and restored to a base band signal. The conventional image enhancement circuit using the glass delay line as the 1 HDL circuit requires a great number of parts as described above and is expensive.
When a CCD is employed, a clock driver for driving the CCD is necessary and this circuit must actuate an electrode capacitance of usually several of hundreds of pF at a frequency of approximately ten MHz, resulting in a large-scale circuit and great power consumption. In addition, low-pass filters must be provided for input and output sides and the CCD per se is expensive. Consequently, the image enhancement circuit with the CCD also suffers from high cost like the image enhancement circuit with the glass delay line.